Kerala PSC Range Forest Officer – Forest and Wildlife – (Electronics Engineering) Previous Question Paper – 048/2025

The Commission publishes this paper without an answer key, so no answers are shown.

1. How must the two transistor junctions be biased for proper transistor amplifier operation? What is the source of leakage current in a transistor? For CB configuration, determine α dc if I E = 2.7 mA and I B = 19 μA . (5)

2. What is the significant difference in the construction of an enhancement type MOSFET and a depletion type MOSFET? Sketch the basic construction of an n-channel depletion type MOSFET, apply the proper drain-to-source voltage and sketch the flow of electrons for VGS = 0V . (5)

3. Explain the principle of operation of thermistor. A thermistor has a resistance temperature coefficient of –5% over a temperature range of 35°C to 60°C. If the resistance of the thermistor is 90 Ω at 35°C, what is the resistance at 45°C. (5)

4. With a neat sketch, explain the working principle of Hall effect transducer. List any two applications of Hall effect transducer. A Hall effect transducer is used for the measurement of magnetic field of 0.7 Wb/m2. The 2mm thick slab is made of Bismuth for which the Hall’s coefficient is − 1 × 10 −6 Vm/(A − Wbm −2 ) and the current is 4A. Determine the output voltage. (5)

5. A combinational logic circuit with three inputs ( A , B , C ) and one output (F ) is defined by the Boolean function F ( A , B , C ) =  (0, 3, 5, 6) . Examine the feasibility of implementing this Boolean function F ( A , B , C ) using a 4:1 multiplexer. If it is possible, provide a detailed circuit diagram that illustrates how to connect the input variables ( A , B ,C ) to the select and data lines of the 4:1 multiplexer using any necessary logic gates. If it is not possible, explain the reason why. (5)

6. A digital system utilizes a cascaded arrangement of single-digit BCD adders to perform additions on multi-digit BCD numbers.
(a) Use your understanding of BCD addition and carry propagation to
explain how the carry-out signal from one single-digit BCD adder stage is utilized as the carry-in signal for the next higher-order BCD adder stage when adding multi-digit BCD numbers.
(b) Analyze a scenario where two 2-digit BCD numbers, 39 and 18, are
added using two cascaded single-digit BCD adders. Trace the flow of data and carry signals through both adder stages, highlighting the intermediate binary sums and the application of the correction logic in each stage. (5)

7. A digital system requires a modulo-1024 counter (which can be implemented using a 10-bitcounter) to be clocked at a frequency of 10 MHz. The design team is considering using either an asynchronous (ripple) counter built with commercially available J-K flip-flops or a synchronous counter.
(a) Analyze the potential limitations of using an asynchronous counter
with J-K flip-flops that have a maximum propagation delay of 15 ns each for this application. Specifically, calculate the maximum operating frequency achievable with this asynchronous design and discuss whether it meets the system requirement of 10 MHz.
(b) Why would a synchronous counter be preferred over an asynchronous
counter for a 10 MHz application, considering that the flip-flops used in either design have a maximum propagation delay of 15 ns? (5)

8. A student is using a two-input TTL NAND gate IC in a digital logic experiment. They connect both inputs of one of the NAND gates to a HIGH logic level (+5V).
(a) Draw the internal circuitry of a standard TTL NAND gate to predict
the state (HIGH or LOW) of the output of this NAND gate under these input conditions. Explain your answer by detailing the conduction (ON/OFF) stages of the relevant transistors within the NAND gate and how these states lead to the predicted output level.
(b) Analyze the current flow within the TTL NAND gate when both
inputs are held HIGH. Describe the states (ON or OFF) of the key transistors in the output stage (totem-pole configuration) and explain the path of current that determines the output voltage level. What is the expected approximate voltage level at the output in this state? (5)

9. Find Norton’s equivalent circuit parameters of the given circuit. (5)

10. Using superposition method, find the current I in the circuit below. (5)

11. For the given circuit, determine the value of load impedance so that
maximum power is transferred through the terminals a and b. (5)

12. Find the Z parameters of the given network. State whether reciprocity
condition is satisfied in the network. (5)

13. Input to a linear delta modulator is a sinusoidal signal whose frequency can vary from 200 hz to 4000 hz. The input is sampled at 8 times the Nyquist rate. The peak amplitude of the sinusoidal signal is 1 volt.
(a) Determine the minimum value of the step size in order to avoid slope
overload when the input signal frequency is 800 hz.
(b) What is the peak amplitude of the input signal, to just overload the
modulator, when the input signal frequency is 200 hz?
(c) Is the modulator overloaded when the input signal frequency is
400 hz? (5)

14. For an amplitude modulation double side Band full carrier wave, with a peak unmodulated carrier voltage of 10V and load resistance of 10 ohm, the modulation index is 0.5. Assume that both the carrier and modulating signals are sinusoidal.
(a) Write the time equation for the modulated signal.
(b) Find the rms power of the carrier and total rms power of modulated
wave. (5)

15. Explain the generation and detection of coherent binary PSK signals. (5)

16. IF Input
Figure shows the first stage of a super heterodyne receiver. The desired input signal is at a frequency of 700 Mhz. The LO freq is 1 Ghz. The mixer is an ideal multiplier with a gain independent of frequency. A BPF is used to select IF output at 300 Mhz.
(a) What is the image freq. of desired input?
(b) A LPF can be used before the mixer to reject the image frequency. If a
perfect rejection of the image is desired, what type of LPF should be employed?
(c) The input in figure is corrupted by an undesired 750 Mhz signal,
which has the same amplitude as those of desired signal at 700 Mhz. Let the BPF be of second order. At the BPF output, the undesired signal should be 20 dB below the desired signal. Calculate the Q required for the BPF. (5)

17. What is the fundamental period of the discrete time signal? x[n] = e^(j(2π/3)n) + e^(j(3π/4)n) (5)

18. If x₁(t) = 100 cos(2π1000t) and x₂(t) = 50 sin(2π500t), what is the Nyquist sampling frequency of x₃(t) = x₁(t)x₂(t)? (5)

19. Using the bilinear transformation s ≈ (2/T)((1 − z⁻¹)/(1 + z⁻¹)), where T is the sampling period, obtain the z-domain transfer function for a low-pass filter with cutoff frequency 100 rad/s at sampling frequency 50 Hz. The low-pass filter transfer function is G(s) = 100/(s + 100). (5)

20. Consider a 16-bit binary number b15b14b13b12b11b10b9b8b7b6b5 b4b3b2b1b0 whose Q1.15 representation is given by the following expression,
− 20 × b15 + 2−1 × b14 + 2−2 × b13 + … + 2−15 × b0
What will be the Q1.15 representation of the hexadecimal number A000 be? (5)

21. Compare MOSFETs with BJTs. (5)

22. Substantiate the behavior of frequency response of an RC coupled amplifier considering.
(a) low frequency region
(b) mid frequency range
(c) high frequency range. (5)

23. Compare series current feedback and series voltage feedback topologies. (5)

24. Differentiate between dc load line and ac load line in the analysis of a BJT with emitter resistor and emitter bypass capacitor. (5)

25. Explain internal program memory and data memory of 8051. (5)

26. 1d, 2d, 3d → driver for 1, 2, 3 1' d' , 2' d' , 3' d' → driver for 1' , 2' , 3'
Fig A is a 3φ voltage source inverter (VSI) and it is controlled via 8051 processor. Write an algorithm to generate pulses for the inverter. Pulse pattern is explained below.
Generated pulses from the processor will be fed to the driver and the driver circuit amplify the pulse and used to turn the status of the power device in the inverter to ‘‘ON’’ or ‘‘OFF’’ state. (5)

27. Explain the addressing modes of 8051. (5)

28. Explain the data processing instructions pertaining to ‘ARM ’ processor. (5)

29. Determine the voltage v1 ,v2 and v0 for the circuit shown below.
10 kΩ
0.6 mA v1 v0
40 kΩ v2 60 kΩ (5)

30. Design an op-amp based amplifier circuit with two inputs and two outputs that can provide the sum (Vsum = v1 + v2 ) and the difference (Vdif = v1 − v2 ) . Where v1 and v2 are two inputs respectively. Use only two op-amps and minimum number of components. (5)

31. A typical strain gauge signal conditioning circuit is shown below. Prove that the output v0 of the circuit is linear with respect to the δ , where δ is the ratio of change in resistance to the original resistance. (5)

32. Design a three-input instrumentation amplifier and derive its output in terms of the input voltages. (5)

33. Find the step response of G(s) = 10/(s + 20) for a step input of magnitude 0.1. (5)

34. F(s) = (s + k₂)/(s⁴ + 2s³ + 2s² + 2s − k₁), where k₁ and k₂ are real. Find all values of k₁ and k₂ for which the system is always stable, with justification. (5)

35. For the state space representation of the system given by [ẋ₁; ẋ₂] = [[−δ, 0], [0, δ]][x₁; x₂] + [1; 1]u, y = [1 1][x₁; x₂] + u, obtain the transfer function in terms of δ, where δ is a constant real number. (5)

36. With suitable justifications obtain the condition to be satisfied by α and φ, for the given system described by ẍ₁ = 2x₁ + 5x₂, ẍ₂ = 4x₁ + 7x₂ + αu, y = φx₁, to be both controllable and observable; use Kalman’s test. Here, x₁ and x₂ are state variables, u is the control input, y is the output, and α and φ are real numbers. (5)

37. How are reflex Klystron oscillators are different from other cavity resonators? (5)

38. Explain the structure and working principle of an Inverted-F Antenna (IFA) used in mobile phones. (5)

39. The TCP/IP protocol suite is the foundation of modern internet communication. Discuss its layered architecture, explaining the functionalities of each layer. How does the suite ensure reliable data transmission across networks and what mechanisms are employed to handle errors, congestion and security threats? (5)

40. What are the key factors contributing to signal attenuation in optical fibers, and what advanced strategies and technologies can be employed to mitigate these losses effectively?
_________________ (5)