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1. What is Fill Factor (FF) in solar PV cell operation 7 Illustrate it using power-voltage curve of solar PV cell. (4)
2. What is Charge-Coupled Device (CCD) sensor 2 How CCD sensor is different from CMOS sensors 7 (4)
3. For the following circuit, find V_AB by suitable method. The outer network has a 100∠0° V source on the left, series impedances j3 and 5 across the top, a 150∠0° V source on the right, and series impedances 5 and −j3 across the bottom; a 100 + j200 V source is connected across the bottom nodes. The left inner branch from top to bottom is 1, j3, node A, −j3, 1; the right inner branch is 1, −j2, node B, 2, j2. (5)
4. Design a series voltage regulator for an output voltage of 5V. Input voltage is in the range of 6.6V to 10.6V. Assume fixed output current of 50 mA, transistor gain of 50, minimum Zener current of 9 mA and maximum Zener current of 49 mA. (4)
5. A 6 bit DAC has a step size of 10 mV. Determine the full-scale output voltage and percentage resolution. (4)
6. Explain the operation of execution of the 8085 instruction "MOV r, M" with the description of all the relevant pins (signals) of the microprocessor. (4)
7. Derive radar range equation. (4)
8. A multimode graded index fiber exhibits total pulse broadening of 0.2 usec over a distance of 20 Km. Estimate (i) The maximum possible bandwidth on the link assuming no inter symbol interference.
(ii) The pulse dispersion per unit length. (4)
9. An SCR in forward blocking has V_A = 25 V, I_G = 1 μA and I_CBO1 = I_CBO2 = 50 nA. If α₁ = 0.5 and α₂ = 0.2, find anode current I_A and dc resistance. (4)
10. Determine the maximum sensitivity of 5 cm, 5 watts single turn 360° potentiometers of total resistance of 100 Ω and 1000 Ω. (4)
11. In an NMOS transistor W/L = 20, μC_ox = 100 μA/V² and V_t = 0.5 V. Find the value of V_GS required to operate the device as a 1 kΩ resistor at small V_DS operation. (6)
12. In a typical constant field CMOS scaling process, the channel dimension is scaled by 1/2 and the oxide thickness and supply voltage are scaled by 1/3. Find the scaling in
i) Gate area
ii) Gate capacitance
iii) Carrier density in the channel. (6)
13. An input x[n] = δ[n] + 2u[n − 1] − u[n − 4] − u[n − 5] is applied to an LTI system with h[n] = {1/2, −1/2}. Determine the output and state, with mathematical explanation, whether h is low-pass or high-pass. (5)
14. Design a summing amplifier with voltage gain of 10 using standard Op-amp to add two voltages. The input impedance should be 100 k. Find the input currents and output voltage when the input voltages are 1V and -2V. (6)
15. For an N-bit adder, G_i (Carry Generate) and P_i (Carry Propagate) are expressed as follows:
P_i = A_i ⊕ B_i
G_i = A_iB_i
Give the generalized expression for output carry C_{i+1}. If carry C_n is computed as a function of P_i, G_i, C_0 which is independent of other internal carries, then find the number of ‘AND’ gates required for C_2 computation. (6)
16. a] Explain the hardware mechanism provided in 8051 microcontroller to handle external interrupts with the status of relevant SFRs.
b) Write an assembly language program to do the conversion of hexadecimal numbers to BCD numbers
using a subroutine for 8051 microcontroller. (6)
17. Briefly explain inconsistency of Ampere's circuital law and how Maxwell modified it. (6)
18. A 1.5 MHz information signal with a dynamic range of 64 mW is sampled, quantized and encoded using a direct binary code. The quantization is linear with 512 levels. Determine maximum possible bit deviation and amplitude of one quantization level.
-3 (6)
19. Reduce the system shown in Fig. 19 to a single transfer function. R(S) enters the first summing point positively and feedback V₆(S) negatively; its output V₁(S) passes through G₁(S) to V₂(S). The second summing point combines V₂(S) positively and V₇(S) negatively to form V₃(S). V₃(S) passes through G₂(S) to V₄(S), while a parallel branch through H₅(S) enters the third summing point positively. The third summing point receives V₄(S) negatively and feedback V₈(S) negatively, producing V₅(S), which passes through G₃(S) to C(S). Feedback paths are V₄(S) through H₂(S) to V₇(S), C(S) through H₃(S) to V₈(S), and V₄(S) through H₄(S) and H₁(S) to V₆(S). (6)
20. A piezoelectric transducer has a capacitance of 1000 pF and a charge sensitivity of 4 × 10⁻⁶ coulombs/cm. The connecting cable has a capacitance of 400 pF. The display device has an input impedance of 1 MΩ resistance and 50 pF capacitance connected in parallel.
i) What is the voltage sensitivity of the piezoelectric transducer alone?
ii) What is the high frequency sensitivity in V/cm of the entire system?
iii) What is the lowest frequency that can be measured with 2% error? (6)
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